Omnivision examiner use only

　　2005 china career fair exam

　　1 logic design

　　1.there is a fifo design which the clock of data input is running at100mhz,while the clock of data output is running at 80mhz.the inputdata is a fix pattern .800 input clocks carry in 800 datacontinuously,and the other 200 clocks carry in no data.how big the fifoshould be in order to avoid data over/under_run?please select theminimum depth below to meet the requirement.

　　A.160 b.200 c.800 d .1000

　　2.supposedly there is acombinational circuit between two registersdriven by a clock.what will you do if the delay of the combinationalcircuit is greater than the clock signal?

　　a.to reduce clock frequency b.to increase clock frequency

　　c.to make it pipelining d to make it multi_cycle

　　3.which of the follow circuits can generate gitch free gated_clk?

　　a.always@(posedge clk) gated <=en;assign gated_clk=gated&~clk;

　　b.always@(negedge clk) gated <=en;assign gated_clk=gated&~clk;

　　c.always@(posedge clk) gated <=en;assign gated_clk=gated|~clk;

　　d.always@(negedge clk) gated <=en;assign gated_clk=gated|~clk;

　　4.you’re working on a specification of a system with some digitalparameters.each parameter has min,typ and max columns.which columnwould you put setup and hold time?

　　a.setup time in max,hold time in min

　　b.setup time in min,hold time in max

　　c.both in max

　　d.both in min

　　5.there are 3 ants at 3corners of a triangle. They randomly startmoving towards another corner.what is the probability that won’tcollide?

　　a.0

　　b.1/8

　　c/1/4

　　d.1/3

　　6.if you look at a clock and the time is 3:15.what is angle between the hour and the minute hand?

　　a.0

　　b.360/48

　　3.360/12

　　d.360/4

　　7.how many times per day a clock’s hands overlap?

　　a.11

　　b.22

　　c.24

　　d.26

　　8.d flip-flop :t_setup=3 ns; t_hold =1 ns; t_ck2q=1ns.what is the max clock frequency the circuit can handle?

　　A.200mhz

　　b.250mhz

　　c.500mhz

　　d.1ghz

　　2.physical design

　　1.before tape-out,which routine check should be performed for your layout database in 0.18 um process?

　　a.drc

　　b.lvs

　　c.drc&antenna

　　e.simulation

　　2.how to fix antenna effect?

　　a.make the wire wider and shorter

　　b.change lower metal to upper metal

　　c.connect with diode of metal and diffusion

　　d.change upper metal to lower metal

　　e.b&c

　　3.please expain lvs

　　a.logic versus schematic

　　b.layout versus schematic

　　c.layout via synthesis

　　d.logic via synthesis

　　4.how to control clock skew?

　　a.get balanced clock tree

　　b.decrease the fanout

　　c.add clock buffer evenly